Brekhov Oleg Mikhaylovich, Doctor of engineering sciences, professor, head of sub-department of computing machines, systems and networks, Moscow Aviation Institute (National research university) (4 Volokolamskoe highway, Moscow, Russia), email@example.com
Ratnikov Maksim Olegovich, Postgraduate student, Moscow Aviation Institute (National research university) (4 Volokolamskoe highway, Moscow, Russia), firstname.lastname@example.org
Background. At designing of fault tolerance FPGA-based systems a great role played by the correct choice of hardware platforms and methods of fault tolerance ensuring. The task is complicated by the need to make this choice in the early stages of development. The aim of the article is to analyze architectural methods of fault tolerance ensuring implemented on different FPGA.
Materials and methods. The paper proposes a new approach to architectural analysis of fault tolerance ensuring methods which develops an idea of using shift registers as a test system. It also allows to carry out the analysis at the early stages of development. This method involves the comparison of characteristics of the base testing system and testing systems protected by the analyzed methods. These systems are implemented in the FPGA, after that one should assesse the probability of an un-recoverable failure. On the basis of these data one may draw a conclusion about the efficiency of these methods.
Results. The authors have developed a new methodology for analyzing architec-tural methods of fault tolerance ensuring. The application of the technique is shown in the following methods’ analysis: block-based TMR, system-based TMR and block-based Hamming-based protection, which is implemented on two different FPGA.
Conclusions. The analysis showed that the optimal method in the given condi-tions according to the criterion of fault-tolerance is the block-based TMR.
FPGA testing, FPGA screening test, FPGA environment test, pipelined function, CRC, self-correcting code, Hamming codes.
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